This invention relates to controlling transfers of data between two processors, for example, a programmable general-purpose (host) processor and a programmable signal processor cooperating to perform the functions of a modem.
In such modems, signal processing e.g., filtering, modulation, and demodulation, are assigned to the signal processor which is designed to perform those tasks quickly and efficiently. The host processor maintains overall control, supervises the signal processor, and handles interactions with the operator and with the devices which supply and use the information carried over the channel to which the modem is connected. In performing these tasks, data must frequently be transferred back and forth between the data buses of the respective processors.
One way of controlling the data transfer is to connect a pair of registers between the data buses, one register for each direction of data transfer. To complete a data transfer, the processor supplying the data loads it into the proper register and interrupts the other processor (using a special interrupt signal). The other processor then jumps from the instruction it is currently executing to a routine of instructions each of which must be fetched, decoded, and executed in order for the interrupted processor to collect the data from the proper register and acknowledge receipt of the data so that another piece of information may be transferred. Ultimately the interrupted processor jumps back to the instruction which was pending at the time of the interruption. Thus, the processors must execute several instructions in order to complete a single data transfer.
By replacing each register with a first-in first-out (FIFO) buffer memory several pieces of data can be queued up in each direction thus eliminating the need for an interrupt (or other handshake) for each data transfer.
By using a dual-port read-write memory in place of the FIFO buffer, multiple queues can be established in each of the two directions by allocating segments of the memory for use as circular FIFO buffers, thus enhancing flexibility. Input and output pointers and FIFO depth counters must be maintained by each processor to control the memory, at a substantial cost in processor time.
In other systems two or more processors share both program and data memories. In some cases one of the processors is a specialized co-processor used in parallel with a general-purpose microprocessor. The co-processor executes only a certain class of instructions, e.g., floating-point arithmetic, thus relieving the general-purpose microprocessor's load and enhancing its performance. Simultaneous parallel operation of the two processors in such a system requires queueing the instructions to, and the results from, the specialized processor.